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ADE7854/ADE7858/ADE7868/ADE7878
Data Sheet
Register
Bit
Bit Length During
Default
Address
0x43B9 to
0x43BE
0x43BF
0x43C0
0x43C1
0x43C2
0x43C3
0x43C4
0x43C5
0x43C6
0x43C7 to
0x43FF
Name
Reserved
ISUM
AIRMS
AVRMS
BIRMS
BVRMS
CIRMS
CVRMS
NIRMS
Reserved
R/W 1
N/A 4
R
R
R
R
R
R
R
R
N/A 4
Length
N/A 4
28
24
24
24
24
24
24
24
N/A 4
Communication 2
N/A 4
32 ZP
32 ZP
32 ZP
32 ZP
32 ZP
32 ZP
32 ZP
32 ZP
N/A 4
Type 3
N/A 4
S
S
S
S
S
S
S
S
N/A 4
Value
0x000000
N/A 4
N/A 4
N/A 4
N/A 4
N/A 4
N/A 4
N/A 4
N/A 4
N/A 4
Description
These memory locations should be kept
at 0x000000 for proper operation.
Sum of IAWV, IBWV, and ICWV registers
( ADE7868 and ADE7878 only).
Phase A current rms value.
Phase A voltage rms value.
Phase B current rms value.
Phase B voltage rms value.
Phase C current rms value.
Phase C voltage rms value.
Neutral current rms value ( ADE7868 and
ADE7878 only).
These memory locations should not be
written for proper operation.
1
2
3
4
R is read, and W is write.
32 ZPSE = 24-bit signed register that is transmitted as a 32-bit word with four MSBs padded with 0s and sign extended to 28 bits. Whereas 32 ZP = 28- or 24-bit signed
or unsigned register that is transmitted as a 32-bit word with four MSBs or eight MSBs, respectively, padded with 0s.
U is unsigned register, and S is signed register in twos complement format.
N/A means not applicable.
Table 31. Internal DSP Memory RAM Registers
Address
0xE203
0xE228
Register
Name
Reserved
Run
R/W 1
R/W
R/W
Bit
Length
16
16
Bit Length
During
Communication
16
16
Type 2
U
U
Default
Value
0x0000
0x0000
Description
This memory location should not be written for
proper operation.
Run register starts and stops the DSP. See the
Digital Signal Processor section for more details.
1
2
R is read, and W is write.
U is unsigned register, and S is signed register in twos complement format.
Table 32. Billable Registers
Address
0xE400
0xE401
0xE402
0xE403
0xE404
0xE405
0xE406
0xE407
Register
Name
AWATTHR
BWATTHR
CWATTHR
AFWATTHR
BFWATTHR
CFWATTHR
AVARHR
BVARHR
R/W 1, 2
R
R
R
R
R
R
R
R
Bit
Length 2
32
32
32
32
32
32
32
32
Bit Length
During
Communication 2
32
32
32
32
32
32
32
32
Type 2, 3
S
S
S
S
S
S
S
S
Default
Value
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
Description
Phase A total active energy accumulation.
Phase B total active energy accumulation.
Phase C total active energy accumulation.
Phase A fundamental active energy
accumulation ( ADE7878 only).
Phase B fundamental active energy
accumulation ( ADE7878 only).
Phase C fundamental active energy
accumulation ( ADE7878 only).
Phase A total reactive energy accumulation
( ADE7858 , ADE7868 , and ADE7878 only).
Phase B total reactive energy accumulation
( ADE7858 , ADE7868 , and ADE7878 only).
0xE408
0xE409
0xE40A
CVARHR
AFVARHR
BFVARHR
R
R
R
32
32
32
32
32
32
S
S
S
0x00000000
0x00000000
0x00000000
Phase C total reactive energy accumulation
( ADE7858 , ADE7868 , and ADE7878 only).
Phase A fundamental reactive energy
accumulation ( ADE7878 only).
Phase B fundamental reactive energy
accumulation ( ADE7878 only).
0xE40B
CFVARHR
R
32
32
S
0x00000000
Phase C fundamental reactive energy
accumulation ( ADE7878 only).
Rev. H | Page 82 of 100
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